1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to the timing constraints associated with signals propagating through an integrated circuit.
2. Description of the Prior Art
It is known within integrated circuits that certain portions of the integrated circuit represent critical paths for processing signals. Such critical paths may, for example, represent processing bottlenecks which restrict the maximum processing speed which can be achieved if they operate too slowly, or may be paths, such as timing paths used within self-timed circuits, which will cause incorrect operation if they operate too quickly. Existing circuit design and synthesis tools are able to identify such critical paths and simulate their operation to determine their typical, lowest and highest path delay when the integrated circuit is manufactured.
It will be appreciated that variations in the manufacture of integrated circuits produces variations in path delay through critical paths. Thus, while an integrated circuit may be designed such that the critical paths have a typical path delay which will produce correct operation, the variations produced in manufacturing may mean that some of these critical paths operate either too quickly or too slowly and the integrated circuit concerned will not function correctly. This reduces the yield of correctly operating integrated circuits produced by the manufacturing process. These problems are becoming greater as process geometry sizes are reducing since the degree of variation due to manufacturing increases at smaller process geometry sizes. There is a further problem that the ageing of integrated circuits can change path delays and take these outside an acceptable range causing the integrated to fail when in use.